1. Field of the Invention
The present invention relates to an analog-to-digital converter (ADC), and more particularly to a folding and interpolating ADC and a method of converting an analog signal into a digital signal.
2. Description of the Related Art
As demand for wideband digital communications has increased, demand for an analog-to-digital converter (ADC) that can operate faster with better resolution has also increased. Generally, the ADC that operates at a high speed can implement a method such as a flash method, a folding and interpolating method, and a pipeline method.
The folding and interpolating method has advantages including 8-bit through 10-bit resolution, one-step conversion, low power consumption and a small area of an operating system. However, the folding and interpolating method has disadvantages including an increased folding factor in proportion to the resolution of the ADC. The increased folding factor results increases a speed of the ADC, thereby causing a non-linearity of the ADC.
Recent research has been devoted to development of a cascaded folding and interpolating ADC, in which folding stages with a small folding factor are cascade-connected in lieu of using a single folding stage with a large folding factor. One of the cascaded folding and interpolating ADCs is disclosed in Korean Patent Laid-Open Publication No. 2004-26907.
In accordance with the above, the cascaded folding and interpolating ADC adopts an equalization method in a preamp stage and includes a series of resistors for an output operation of first and second folding circuits that are coupled in a cascade fashion so as to interpolate signals.
An input signal of the first folding circuit is interpolated in the preamp stage by using the equalization method. Since the input signal of the first folding circuit can have an interpolating error, an increase in a resolution and a conversion speed of the cascaded folding and interpolating ADC is limited due to an increase in the interpolating error.